Memory access tracing is a program analysis technique with many different applications, ranging from architectural simulation to (on-line) data placement optimization and security enforcement. In this article we propose a memory access tracing approach based on static x86 binary instrumentation. Unlike non-selective schemes, which instrument all the memory access instructions, our proposal selectively instruments a subset of those instructions that are the most (or fully) representative of the actual memory access pattern. The selection of the memory access instructions to be instrumented is based on a new method, which clusters instructions on the basis of their compile/link-time observable address expressions and selects representatives of these clusters. This allows for reducing the runtime cost for running instrumented code, while still enabling high accuracy in the determination of memory accesses. The trade-off between overhead and precision of the tracing process is user-tunable, so that it can be set depending on the final objective of memory access tracing (say on-line vs off-line exploitation). Additionally, our approach can track memory access at different granularity (e.g., virtual-pages or cache line-sized buffers), thus having applications in a variety of different contexts. The effectiveness of our proposal is demonstrated via experiments with applications taken from the PARSEC benchmark suite.

Configurable and efficient memory access tracing via selective expression-based x86 binary instrumentation / Economo, Simone; Cingolani, Davide; Pellegrini, Alessandro; Quaglia, Francesco. - (2016), pp. 261-270. (Intervento presentato al convegno 24th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS 2016 tenutosi a London; United Kingdom nel 2016) [10.1109/MASCOTS.2016.69].

Configurable and efficient memory access tracing via selective expression-based x86 binary instrumentation

ECONOMO, SIMONE
;
CINGOLANI, DAVIDE
;
PELLEGRINI, ALESSANDRO
;
QUAGLIA, Francesco
2016

Abstract

Memory access tracing is a program analysis technique with many different applications, ranging from architectural simulation to (on-line) data placement optimization and security enforcement. In this article we propose a memory access tracing approach based on static x86 binary instrumentation. Unlike non-selective schemes, which instrument all the memory access instructions, our proposal selectively instruments a subset of those instructions that are the most (or fully) representative of the actual memory access pattern. The selection of the memory access instructions to be instrumented is based on a new method, which clusters instructions on the basis of their compile/link-time observable address expressions and selects representatives of these clusters. This allows for reducing the runtime cost for running instrumented code, while still enabling high accuracy in the determination of memory accesses. The trade-off between overhead and precision of the tracing process is user-tunable, so that it can be set depending on the final objective of memory access tracing (say on-line vs off-line exploitation). Additionally, our approach can track memory access at different granularity (e.g., virtual-pages or cache line-sized buffers), thus having applications in a variety of different contexts. The effectiveness of our proposal is demonstrated via experiments with applications taken from the PARSEC benchmark suite.
2016
24th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS 2016
Memory tracing; Program profiling; Static instrumentation; X86 ISA; Modeling and Simulation
04 Pubblicazione in atti di convegno::04b Atto di convegno in volume
Configurable and efficient memory access tracing via selective expression-based x86 binary instrumentation / Economo, Simone; Cingolani, Davide; Pellegrini, Alessandro; Quaglia, Francesco. - (2016), pp. 261-270. (Intervento presentato al convegno 24th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS 2016 tenutosi a London; United Kingdom nel 2016) [10.1109/MASCOTS.2016.69].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/931681
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