Synchronous early-completion-prediction adders (ECPAs) are used for high clock rate and high-precision DSP datapaths, as they allow a dominant amount of single-cycle operations even if the worst-case carry propagation delay is longer than the clock period. Previous works have also demonstrated ECPA advantages for average leakage reduction and NBTI effects reduction in nanoscale CMOS technologies. This paper illustrates a general systematic methodology to design ECPA units, targeting nanoscale CMOS technologies, which is not available in the current literature yet. The method is fully compatible with standard VLSI macrocell design tools and standard adder structures and includes automatic definition of critical test patterns for postlayout verification. A design example is included, reporting speed and power data superior to previous works. © 2013 Mauro Olivieri and Antonio Mastrandrea.

A general design methodology for synchronous early-completion-prediction adders in Nano-CMOS DSP architectures / Olivieri, Mauro; Mastrandrea, Antonio. - In: VLSI DESIGN. - ISSN 1065-514X. - STAMPA. - 2013:(2013), pp. 1-12. [10.1155/2013/785281]

A general design methodology for synchronous early-completion-prediction adders in Nano-CMOS DSP architectures

OLIVIERI, Mauro;MASTRANDREA, ANTONIO
2013

Abstract

Synchronous early-completion-prediction adders (ECPAs) are used for high clock rate and high-precision DSP datapaths, as they allow a dominant amount of single-cycle operations even if the worst-case carry propagation delay is longer than the clock period. Previous works have also demonstrated ECPA advantages for average leakage reduction and NBTI effects reduction in nanoscale CMOS technologies. This paper illustrates a general systematic methodology to design ECPA units, targeting nanoscale CMOS technologies, which is not available in the current literature yet. The method is fully compatible with standard VLSI macrocell design tools and standard adder structures and includes automatic definition of critical test patterns for postlayout verification. A design example is included, reporting speed and power data superior to previous works. © 2013 Mauro Olivieri and Antonio Mastrandrea.
2013
01 Pubblicazione su rivista::01a Articolo in rivista
A general design methodology for synchronous early-completion-prediction adders in Nano-CMOS DSP architectures / Olivieri, Mauro; Mastrandrea, Antonio. - In: VLSI DESIGN. - ISSN 1065-514X. - STAMPA. - 2013:(2013), pp. 1-12. [10.1155/2013/785281]
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/509832
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