In nano-scale digital CMOS ICs, technology parameter variation limits the usefulness of traditional corner-based timing simulation in favor of statistical simulation. Yet, logic level delay modeling featuring technology variation aware timing is an open challenge. We present a new semi-empirical delay model of digital CMOS cells, accounting for input slope and technology parameters, featuring Spice-level accuracy and full suitability for logic level (i.e. fast) statistical timing simulation in an HDL environment. The approach has been tested against Spice BSIM4 targeting a library of 272 standard cells. © 2011 IEEE.
A delay model allowing nano-CMOS standard cells statistical simulation at the logic level / Mastrandrea, Antonio; Menichelli, Francesco; Olivieri, Mauro. - (2011), pp. 217-220. (Intervento presentato al convegno 2011 7th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2011 tenutosi a Madonna di Campiglio, Trento nel 3 July 2011 - 7 July 2011) [10.1109/prime.2011.5966256].
A delay model allowing nano-CMOS standard cells statistical simulation at the logic level
MASTRANDREA, ANTONIO;MENICHELLI, FRANCESCO;OLIVIERI, Mauro
2011
Abstract
In nano-scale digital CMOS ICs, technology parameter variation limits the usefulness of traditional corner-based timing simulation in favor of statistical simulation. Yet, logic level delay modeling featuring technology variation aware timing is an open challenge. We present a new semi-empirical delay model of digital CMOS cells, accounting for input slope and technology parameters, featuring Spice-level accuracy and full suitability for logic level (i.e. fast) statistical timing simulation in an HDL environment. The approach has been tested against Spice BSIM4 targeting a library of 272 standard cells. © 2011 IEEE.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
