An MDAC architecture with low sensitivity to finite opamp gain

An architecture for MDAC stages with low sensitivity to finite opamp gain is proposed, that allows designing high-precision pipeline ADCs in deep submicron technologies. The standard MDAC architecture is modified by inserting a voltage follower in the feedback path, and zero gain error is achieved if a relationship between the gain of the main opamp and of the opamp used in the voltage follower is satisfied. Simulations using 65-nm CMOS technology are presented to assess the validity of the proposed solution, that allows achieving low sensitivity to finite opamp gain even in case of mismatches in the relationship between the gains of the opamps. © 2011 IEEE.