Process variations are becoming a paramount design problem in nano-scale VLSI. We present a framework for the statistical model of logic gates that describes both inter-die and intra-die variations of performance parameters such as propagation delay and leakage currents. This allows fast but accurate behavioral-level Monte-Carlo simulations, that could be useful for full-custom digital design optimization and yield prediction, and enables the development of a yield-aware digital design flow. The model can incorporate correlation between mismatch parameters and dependence on distance and position, and can be extracted by fitting of Monte-Carlo transistor level simulations. An example implementation using Verilog-A hardware description language in Cadence environment is presented.

A statistical model of logic gates for Monte Carlo simulation including on-chip variation / Centurelli, Francesco; Giancane, Luca; Olivieri, Mauro; Scotti, Giuseppe; Trifiletti, Alessandro. - STAMPA. - 4644:(2007), pp. 516-525. (Intervento presentato al convegno PATMOS 07: 17th International Workshop on Power and Timing Modeling, Optimization and Simulation tenutosi a Goteborg) [10.1007/978-3-540-74442-9_50].

A statistical model of logic gates for Monte Carlo simulation including on-chip variation

CENTURELLI, Francesco;GIANCANE, Luca;OLIVIERI, Mauro;SCOTTI, Giuseppe;TRIFILETTI, Alessandro
2007

Abstract

Process variations are becoming a paramount design problem in nano-scale VLSI. We present a framework for the statistical model of logic gates that describes both inter-die and intra-die variations of performance parameters such as propagation delay and leakage currents. This allows fast but accurate behavioral-level Monte-Carlo simulations, that could be useful for full-custom digital design optimization and yield prediction, and enables the development of a yield-aware digital design flow. The model can incorporate correlation between mismatch parameters and dependence on distance and position, and can be extracted by fitting of Monte-Carlo transistor level simulations. An example implementation using Verilog-A hardware description language in Cadence environment is presented.
2007
PATMOS 07: 17th International Workshop on Power and Timing Modeling, Optimization and Simulation
logic gates; statistical model; digital circuits
04 Pubblicazione in atti di convegno::04b Atto di convegno in volume
A statistical model of logic gates for Monte Carlo simulation including on-chip variation / Centurelli, Francesco; Giancane, Luca; Olivieri, Mauro; Scotti, Giuseppe; Trifiletti, Alessandro. - STAMPA. - 4644:(2007), pp. 516-525. (Intervento presentato al convegno PATMOS 07: 17th International Workshop on Power and Timing Modeling, Optimization and Simulation tenutosi a Goteborg) [10.1007/978-3-540-74442-9_50].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/367810
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