In this study, the latched ring oscillator, previously employed as an entropy source in a True Random Number Generator, is exploited as Physical Unclonable Functions to derive keys. The LRO cell aims to minimize hardware usage on FPGA, particularly with respect to those architecture which exploits ring oscillators. An LRO-based PUF is implemented on an Artix-7 FPGA, occupying only 0.25 Slice/bit, representing cutting-edge efficiency. Evaluation on 16 Artix-7 FPGAs confirms the approach’s effectiveness, achieving a Uniqueness of 48.63%, nominal Reliability of 95.11%, and 0–1 bias of 46.82%.
Exploiting the Latched Ring Oscillator Cell as a Compact PUF Architecture on FPGA / Della Sala, R., Scotti, G.. - 1263:(2025), pp. 29-34. (55th Annual Meeting of the Italian Electronics Society, SIE 2024 Genova Italia ) [10.1007/978-3-031-71518-1_4].
Exploiting the Latched Ring Oscillator Cell as a Compact PUF Architecture on FPGA
Della Sala, Riccardo;Scotti, Giuseppe
2025
Abstract
In this study, the latched ring oscillator, previously employed as an entropy source in a True Random Number Generator, is exploited as Physical Unclonable Functions to derive keys. The LRO cell aims to minimize hardware usage on FPGA, particularly with respect to those architecture which exploits ring oscillators. An LRO-based PUF is implemented on an Artix-7 FPGA, occupying only 0.25 Slice/bit, representing cutting-edge efficiency. Evaluation on 16 Artix-7 FPGAs confirms the approach’s effectiveness, achieving a Uniqueness of 48.63%, nominal Reliability of 95.11%, and 0–1 bias of 46.82%.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
