Ask Less, Get More: On Reducing the Resource Consumption and Improving Statistical Performance of Ring Oscillator PUFs on FPGA

In this work a novel implementation of the Single Slice Ring Oscillator (SS-RO) PUF targeting the AMD Artix-7 FPGA platform is proposed. To derive the optimal implementation, preliminary tests on the FPGA have been carried out by taking into account an ad-hoc bit extraction strategy, which is, along with the proposed FPGA implementation of the SS-RO PUF-cell, the novelty presented in this work. Results have shown that the statistical performance of the PUF in terms of uniqueness and bias of the key is dependent on the bit extraction strategy. Trade-offs among the reliability and the uniqueness of the key have been evaluated, showing that with the proposed technique a state-of-the-art PUF, with a bit error rate of only 2.01% and a uniqueness of about 48.97% in typical conditions, can be obtained.