A hysteresis comparator for ultra-low-voltage asynchronous Sigma-Delta Modulators is presented, featuring a regenerative bulk-based SRAM output stage for rail-to-rail operation and enhanced speed. Simulations show a delay of 35.91 μs, power dissipation of 7.27 nW, and a hysteresis threshold of 4.20 mV. The design exhibits strong resilience under PVT and mismatch variations. An analytical hysteresis model, validated through simulation, closely matches observed behavior. Compared to a state-of-the-art solution, the proposed comparator achieves an up to 2 × faster delay, lower power, and more stable hysteresis, making it well-suited for low-power analog applications in IoT and biomedical systems.
A 0.3V Hysteresis Comparator with Bulk-Based SRAM Output Stage / Nicolini, G., Sala, R.D., Scotti, G.. - (2025), pp. 1-4. (20th International Conference on PhD Research in Microelectronics and Electronics, PRIME 2025 Taormina, Italy ) [10.1109/prime66228.2025.11203337].
A 0.3V Hysteresis Comparator with Bulk-Based SRAM Output Stage
Nicolini, Giovanni;Sala, Riccardo Della;Scotti, Giuseppe
2025
Abstract
A hysteresis comparator for ultra-low-voltage asynchronous Sigma-Delta Modulators is presented, featuring a regenerative bulk-based SRAM output stage for rail-to-rail operation and enhanced speed. Simulations show a delay of 35.91 μs, power dissipation of 7.27 nW, and a hysteresis threshold of 4.20 mV. The design exhibits strong resilience under PVT and mismatch variations. An analytical hysteresis model, validated through simulation, closely matches observed behavior. Compared to a state-of-the-art solution, the proposed comparator achieves an up to 2 × faster delay, lower power, and more stable hysteresis, making it well-suited for low-power analog applications in IoT and biomedical systems.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
