A 0.3V hysteresis comparator with bulk-based SRAM output stage

A hysteresis comparator for ultra-low-voltage asynchronous Sigma-Delta Modulators is presented, featuring a regenerative bulk-based SRAM output stage for rail-to-rail operation and enhanced speed. Simulations show a delay of 35.91 μs, power dissipation of 7.27 nW, and a hysteresis threshold of 4.20 mV. The design exhibits strong resilience under PVT and mismatch variations. An analytical hysteresis model, validated through simulation, closely matches observed behavior. Compared to a state-of-the-art solution, the proposed comparator achieves an up to 2 × faster delay, lower power, and more stable hysteresis, making it well-suited for low-power analog applications in IoT and biomedical systems.