This work presents a bulk-driven operational transconductance amplifier (OTA) designed to operate from a 400mV supply while maintaining nanowatt-level power consumption. The proposed single-stage cascode topology achieves a differential gain close to 75dB, combining a body-driven input pair with output-resistance enhancement through a positive-feedback mechanism. Areplica-bias loop is incorporated to improve robustness to PVT variations without increasing current consumption. The OTA was implemented in a 180nm TSMC CMOS technology, and post-layout simulations demonstrate strong resilience to PVT and device mismatch variations. Afabricated prototype was experimentally characterized, showing a measured DC gain consistent with simulations, a CMRR of 44.5dB and PSRR of 42.5dB at 1Hz, and a voltage offset of approximately 4.5mV, while consuming 1.9 nW of power. Time-domain tests further confirm the OTA’s dynamic performance, including a measured slew rate of 1.02 V/ms for a 200~\mathrm {mV_{pp}} step input. Overall, the results validate the proposed architecture as an energy-efficient and compact solution suitable for ultra-low-power analog front-ends in biomedical and autonomous sensing applications.
A 0.4V 1.9-nW Bulk-Driven Cascode OTA Achieving 75-dB DC Gain With Replica-Bias Assisted PVT Robustness / Della Sala, R., Nicolini, G., Trifiletti, A., Scotti, G.. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS. - ISSN 1549-8328. - (2026), pp. 1-14. [10.1109/TCSI.2026.3679939]
A 0.4V 1.9-nW Bulk-Driven Cascode OTA Achieving 75-dB DC Gain With Replica-Bias Assisted PVT Robustness
Della Sala R.Primo
;Nicolini G.Secondo
;Trifiletti A.;Scotti G.Ultimo
2026
Abstract
This work presents a bulk-driven operational transconductance amplifier (OTA) designed to operate from a 400mV supply while maintaining nanowatt-level power consumption. The proposed single-stage cascode topology achieves a differential gain close to 75dB, combining a body-driven input pair with output-resistance enhancement through a positive-feedback mechanism. Areplica-bias loop is incorporated to improve robustness to PVT variations without increasing current consumption. The OTA was implemented in a 180nm TSMC CMOS technology, and post-layout simulations demonstrate strong resilience to PVT and device mismatch variations. Afabricated prototype was experimentally characterized, showing a measured DC gain consistent with simulations, a CMRR of 44.5dB and PSRR of 42.5dB at 1Hz, and a voltage offset of approximately 4.5mV, while consuming 1.9 nW of power. Time-domain tests further confirm the OTA’s dynamic performance, including a measured slew rate of 1.02 V/ms for a 200~\mathrm {mV_{pp}} step input. Overall, the results validate the proposed architecture as an energy-efficient and compact solution suitable for ultra-low-power analog front-ends in biomedical and autonomous sensing applications.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.


