In this work,a novel bulk-driven OTA capable to operate with a supply voltage as low as 400mV is presented. The proposed single stage topology results in an increased differential gain of about 75dB, while guaranteeing a very low power consumption in the range of 1.8nW. The amplifier exploits a body-driven input stage with a current-mirror-based differential to single-ended converter. The gain of the OTA is boosted thanks to the adoption of a cascode configuration and of a positive feedback loop, which allows to increase the output resistance without adding additional current branches. The CMRR is also improved thanks to the adoption of a replica bias loop which takes track of common-mode voltage variations to adjust the common-mode current, resulting in a CMRR higher than 85dB. The circuit has been designed considering a 180nm CMOS technology from TSMC, and post-layout simulations in the Cadence Virtuoso environment have shown an excellent resilience of the proposed OTA to PVT variations.

A body-driven, 1.8 nW, 75 dB gain, single stage OTA, for ULV and ULP applications / Sala, Riccardo Della; Nicolini, Giovanni; Scotti, Giuseppe. - (2025), pp. 1-5. ( 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 London, gbr ) [10.1109/iscas56072.2025.11043410].

A body-driven, 1.8 nW, 75 dB gain, single stage OTA, for ULV and ULP applications

Sala, Riccardo Della
Primo
;
Nicolini, Giovanni;Scotti, Giuseppe
Ultimo
2025

Abstract

In this work,a novel bulk-driven OTA capable to operate with a supply voltage as low as 400mV is presented. The proposed single stage topology results in an increased differential gain of about 75dB, while guaranteeing a very low power consumption in the range of 1.8nW. The amplifier exploits a body-driven input stage with a current-mirror-based differential to single-ended converter. The gain of the OTA is boosted thanks to the adoption of a cascode configuration and of a positive feedback loop, which allows to increase the output resistance without adding additional current branches. The CMRR is also improved thanks to the adoption of a replica bias loop which takes track of common-mode voltage variations to adjust the common-mode current, resulting in a CMRR higher than 85dB. The circuit has been designed considering a 180nm CMOS technology from TSMC, and post-layout simulations in the Cadence Virtuoso environment have shown an excellent resilience of the proposed OTA to PVT variations.
2025
2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025
Internet of things; inverter-based; OTA; ultra-low power; ultra-low voltage
04 Pubblicazione in atti di convegno::04b Atto di convegno in volume
A body-driven, 1.8 nW, 75 dB gain, single stage OTA, for ULV and ULP applications / Sala, Riccardo Della; Nicolini, Giovanni; Scotti, Giuseppe. - (2025), pp. 1-5. ( 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 London, gbr ) [10.1109/iscas56072.2025.11043410].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/1750327
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