Cascadable complementary SSF-based biquads with 8 GHz cutoff frequency and very low power consumption

Low-pass filters with bandwidths larger than several GHz are required in many applications, such as anti-aliasing filters in high-speed ADCs and pulse-shaping filters in high-speed DACs. In highly integrated applications, low area occupation and power consumption are key specifications, so inductor-less implementations are to be preferred. Furthermore, full CMOS implementations provide an advantage in terms of technology availability and cost. In this paper, we present an inductor-less CMOS biquad stage based on the super source follower topology that provides an 8 GHz cutoff frequency and a low power consumption of 0.42 mW per pole, showing remarkable performance also in terms of bandwidth and dynamic range. The availability of two separate current sources allows independent tuning of natural frequency and quality factor. The stage can be implemented in two complementary ways, exploiting NMOS and PMOS input devices, respectively, thus simplifying cascadability. The two complementary biquads have been implemented in the STMicroelectronics FDSOI 28 nm CMOS process and extensively simulated and provide stable performance under PVT variations and mismatches. The area occupation is about 387.5 μm2 per biquad, one of the lowest in the literature. The figures-of-merit are remarkable, as the filters achieve excellent power efficiency, very low area occupation, and good dynamic range.