On enhancing the throughput of the latched ring oscillator TRNG on FPGA

In this summary, we introduce a new design of the Latched Ring Oscillator (LRO), true-random-number-generator (TRNG) on a 7- Series FPGA, demonstrating the portability of the architecture. The novel design, combined with a novel sampling strategy, allows to enhance performance of the previous work, speeding up the throughput of about 265 times. The proposed LRO-TRNG effectively utilizes both meta- stability, manufacturing variations and accumulated jitter as sources of entropy, resulting in excellent levels of unpredictability and randomness. The TRNG’s performance has been validated with considering NIST and AIS-31 tests. Measurement results indicate that the LRO-TRNG achieves an estimated entropy of approximately 7.99984 per byte (as per the T8 test of the AIS-31) and a throughput of 201 Mbits/s using a 450MHz clock. When compared to existing TRNGs, the LRO-TRNG surpasses most of previously published designs in terms of the through- put attaining a good trade-off among speed and FPGA resources usage.