A 150 MS/s, 10 bit SAR ADC Featuring a Modified Quasi-Monotonic Switching Scheme

This work proposes a novel switching algorithm for capacitive digital-to-analog converters (CDAC) in successive approximation register (SAR) analog-to-digital converters (ADC). The proposed CDAC requires the same number of capacitors and switches as the monotonic switching CDAC while achieving a much smaller output common mode swing. This is obtained by properly alternating upwards and downwards transitions in the CDAC and by temporarily shifting the output common mode voltage. In addition, the common mode voltage to which the CDAC outputs converge can be decoupled from the input common mode of the ADC. As a result, the performance of the converter improves significantly because the behavior of the CDAC can be tailored according to the optimum input common mode of the comparator. The only cost is a slight increase of the average power consumption. The proposed technique has been validated by applying it to a 10 bit, 150 MS/s SAR ADC implemented in a 55 nm technology by STMicroelectronics. Despite the absence of calibration and redundant encoding, the ADC exhibits a signal-to-noise-and-distortion ratio (SNDR) of 56.3 dB while consuming 5.7 mW from a 1 V supply.