We propose a model Hamiltonian for van der Waals tunnel transistors relying on a few physical parameters that we calibrate against DFT band structure calculations. This approach allowed us to develop a fully three-dimensional (3-D) NEGF based simulator and to investigate fundamental and design aspects related to van der Waals tunnel transistors, such as: (a) area and edge tunneling components, and scaling with device area; (b) impact of top gate alignment and back-oxide thickness on the device performance; (c) influence of inelastic phonon scattering on the device operation and sub-threshold swing; (d) benchmarking of switching energy and delay

A computational study of van der Waals tunnel transistors. Fundamental aspects and design challenges / Cao, J; Logoteta, D; Ozkaya, S; Biel, B; Cresti, A; Pala, M; Esseni, D. - (2015), pp. 313-316. (Intervento presentato al convegno International Electron Devices Meeting (IEDM) 2015 tenutosi a Washington, DC; USA) [10.1109/IEDM.2015.7409684].

A computational study of van der Waals tunnel transistors. Fundamental aspects and design challenges

Logoteta D;
2015

Abstract

We propose a model Hamiltonian for van der Waals tunnel transistors relying on a few physical parameters that we calibrate against DFT band structure calculations. This approach allowed us to develop a fully three-dimensional (3-D) NEGF based simulator and to investigate fundamental and design aspects related to van der Waals tunnel transistors, such as: (a) area and edge tunneling components, and scaling with device area; (b) impact of top gate alignment and back-oxide thickness on the device performance; (c) influence of inelastic phonon scattering on the device operation and sub-threshold swing; (d) benchmarking of switching energy and delay
2015
International Electron Devices Meeting (IEDM) 2015
benchmarking; design for testability; electron devices
04 Pubblicazione in atti di convegno::04b Atto di convegno in volume
A computational study of van der Waals tunnel transistors. Fundamental aspects and design challenges / Cao, J; Logoteta, D; Ozkaya, S; Biel, B; Cresti, A; Pala, M; Esseni, D. - (2015), pp. 313-316. (Intervento presentato al convegno International Electron Devices Meeting (IEDM) 2015 tenutosi a Washington, DC; USA) [10.1109/IEDM.2015.7409684].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/1675135
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