In this brief we present a novel, ultra-compact, True Random Number Generator (TRNG) architecture and its FPGA implementation. The proposed Latched Ring Oscillator (LRO) TRNG allows the generation of a TRNG bit from a single FPGA Slice. Despite its very compact structure, the proposed LROTRNG relies on both meta-stability and accumulated jitter as entropy sources, and exhibits very good results in terms of unpredictability and randomness. The proposed architecture has been implemented on Xilinx Spartan-6 devices and the TRNG performances have been extensively validated under supply voltage and temperature variations. Measurements results have shown that the LRO-TRNG exhibits an estimated entropy of about 7.99834 per bit (according to T8 test of the AIS-31) and a throughput of 0.76 Mbits/s with a 50MHz clock. A comparison against the state of the art shows that the proposed LRO-TRNG outperforms most of the previously published TRNGs, in terms of the ratio between throughput and FPGA resources usage.

A Novel Ultra-Compact {FPGA}-Compatible {TRNG} Architecture Exploiting Latched Ring Oscillators / DELLA SALA, Riccardo; Bellizia, Davide; Scotti, Giuseppe. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - 69:3(2022), pp. 1672-1676. [10.1109/tcsii.2021.3121537]

A Novel Ultra-Compact {FPGA}-Compatible {TRNG} Architecture Exploiting Latched Ring Oscillators

Riccardo Della Sala
Primo
;
Davide Bellizia
Secondo
;
Giuseppe Scotti
Ultimo
2022

Abstract

In this brief we present a novel, ultra-compact, True Random Number Generator (TRNG) architecture and its FPGA implementation. The proposed Latched Ring Oscillator (LRO) TRNG allows the generation of a TRNG bit from a single FPGA Slice. Despite its very compact structure, the proposed LROTRNG relies on both meta-stability and accumulated jitter as entropy sources, and exhibits very good results in terms of unpredictability and randomness. The proposed architecture has been implemented on Xilinx Spartan-6 devices and the TRNG performances have been extensively validated under supply voltage and temperature variations. Measurements results have shown that the LRO-TRNG exhibits an estimated entropy of about 7.99834 per bit (according to T8 test of the AIS-31) and a throughput of 0.76 Mbits/s with a 50MHz clock. A comparison against the state of the art shows that the proposed LRO-TRNG outperforms most of the previously published TRNGs, in terms of the ratio between throughput and FPGA resources usage.
2022
TRNGs, field programmable gate array (FPGA), ring oscillators, metastability, jitter.
01 Pubblicazione su rivista::01a Articolo in rivista
A Novel Ultra-Compact {FPGA}-Compatible {TRNG} Architecture Exploiting Latched Ring Oscillators / DELLA SALA, Riccardo; Bellizia, Davide; Scotti, Giuseppe. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - 69:3(2022), pp. 1672-1676. [10.1109/tcsii.2021.3121537]
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/1654880
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