In this brief we introduce a novel lightweight FPGA compatible Physical Unclonable Function (PUF) primitive based on XOR gates. The proposed XOR-PUF is the most compact FPGA-compatible PUF ever presented in the literature, allowing the implementation of four PUF bits in a single Configurable Logic Block (CLB) and providing very good statistical performance. The architecture of the proposed PUF exploits two cross-coupled XOR gates which can be configured to behave as ring oscillators or SRAM cells. A 128-bit weak-PUF block based on the proposed XOR-PUF basic cell has been implemented on Xilinx Spartan-6 and Artix-7 devices and an extensive measurement campaign on 16 FPGA devices for each family has been carried out. Measurement results have shown that the proposed architecture and implementation are able to fit in just 64 Slices (32 CLBs) on both the Spartan-6 and Artix-7 devices without sacrificing statistical performance and guaranteeing a good robustness against supply voltage variations.

A Lightweight {FPGA} Compatible Weak-{PUF} Primitive Based on {XOR} Gates / DELLA SALA, Riccardo; Bellizia, Davide; Scotti, Giuseppe. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - 69:6(2022), pp. 2972-2976. [10.1109/tcsii.2022.3156788]

A Lightweight {FPGA} Compatible Weak-{PUF} Primitive Based on {XOR} Gates

Riccardo Della Sala
Primo
;
Davide Bellizia
Secondo
;
Giuseppe Scotti
Ultimo
2022

Abstract

In this brief we introduce a novel lightweight FPGA compatible Physical Unclonable Function (PUF) primitive based on XOR gates. The proposed XOR-PUF is the most compact FPGA-compatible PUF ever presented in the literature, allowing the implementation of four PUF bits in a single Configurable Logic Block (CLB) and providing very good statistical performance. The architecture of the proposed PUF exploits two cross-coupled XOR gates which can be configured to behave as ring oscillators or SRAM cells. A 128-bit weak-PUF block based on the proposed XOR-PUF basic cell has been implemented on Xilinx Spartan-6 and Artix-7 devices and an extensive measurement campaign on 16 FPGA devices for each family has been carried out. Measurement results have shown that the proposed architecture and implementation are able to fit in just 64 Slices (32 CLBs) on both the Spartan-6 and Artix-7 devices without sacrificing statistical performance and guaranteeing a good robustness against supply voltage variations.
2022
Physical unclonable functions (PUFs), identification generator, metastability, field programmable gate array (FPGA), hardware-security.
01 Pubblicazione su rivista::01a Articolo in rivista
A Lightweight {FPGA} Compatible Weak-{PUF} Primitive Based on {XOR} Gates / DELLA SALA, Riccardo; Bellizia, Davide; Scotti, Giuseppe. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - 69:6(2022), pp. 2972-2976. [10.1109/tcsii.2022.3156788]
File allegati a questo prodotto
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/1654877
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo

Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 7
  • ???jsp.display-item.citation.isi??? 5
social impact