Analytical model of the drain current in amorphous silicon junction field effect transistors

This paper presents an analytical model of a hydrogenated amorphous silicon (a-Si:H) junction field effect transistor (JFET) based on a p-type/intrinsic/n-type stacked structure. The p-doped layer is connected to the transistor gate electrode, while the n-layer acts as the device channel. The analysis shows the effect of the geometrical and physical parameters of the intrinsic and n-doped layers on the transistor characteristics. In particular, the intrinsic layer thickness plays a central role in determining the depletion region of the n-channel and, as a consequence, the device threshold voltage. The drain current behavior achieved with a modeled parametric analysis is in very good agreement with the experimental drain current measured on fabricated JFET, both in triode and pinch-off regions. This demonstrates the model feasibility as an effective tool to design thin film electronic circuit as a sensor signal amplifier based on a-Si:H p-i-n junction.