Generation of oxide traps in Back-Side-Illuminated CMOS image sensors and impact on reliability

A systematic characterization of peripheral transistors in Front-Side and Back-Side-Illuminated CMOS Image Sensors is presented. Experimental results are supported by electrostatic simulations of the gate stack. The out-coming picture is that a distribution of border traps is generated in the gate oxide in the Back-Side configuration during the wafer flipping/bonding/thinning and via opening loop. It shifts the flatband voltage, increases the channel leakage current and alters the oxide electric field. Different reliability tests demonstrate that in the Back-Side-Illuminated configuration lifetime is degraded respect to the Front-Side one, due to the particular features of that trap distribution.