A very-olw-voltage frequency divider in folded MOS current mode logic with complementary n- and p-type flip-flops

In this article, a static frequency divider based on folded MOS current mode logic (FMCML) is presented. The design is based on alternating FMCML flip-flops with complementary pMOS or nMOS input differential pairs since common-mode problems arise by using only one type of FMCML flip-flops. The design is carried out after detailed theoretical modeling and analysis versus the flip-flop bias current, thus allowing defining optimized design strategies for the maximum speed or the minimum power-delay product (PDP). The frequency divider architecture and design strategies are validated considering a commercial 28-nm FDSOI CMOS technology. Postlayout simulations of a divider-by-16 show a maximum frequency of about 12 GHz with 74-μW power consumption for the high-speed design and a maximum frequency of 10 GHz with 53-μW power consumption for the minimum PDP design.