Delay models and design guidelines for MCML gates with resistor or PMOS load

In this paper we present propagation delay models for MCML gates with resistor- or triode-PMOS-based output I–V conversion. The dependence of the parasitic capacitance of triode PMOS devices is accurately evaluated for the first time in the literature. The proposed models are able to accurately predict the propagation delay as a function of the bias current ISS in different design scenarios which require different tradeoffs between speed, area and power efficiency. The proposed models are validated against transistor level simulations referring to a 28 ​nm CMOS process showing a maximum percentage error lower than 6.5%. Based on these models, a comparative analysis is carried out and useful guidelines for the design of MCML gates are proposed.