An improvement of a standard fully differential class-AB symmetrical operational transconductance amplifier (OTA) topology is proposed in this brief to enhance the common-mode behavior. Common-mode behavior could be critical in fully differential class-AB OTAs, where the total current is not fixed and differential to common-mode conversion could therefore be present. A signal proportional to the input commonmode component is generated through a simple low-current auxiliary amplifier and used to modulate a bias voltage, achieving cancellation of the output common-mode component. Simulations in 40-nm CMOS technology show a net improvement of common mode rejection ratio without affecting differential-mode behavior; the increase in area and power consumption is minimal, with a tradeoff between power and settling time. Simulations of a sample-and-hold exploiting the proposed OTA are presented.
A topology of fully differential class-AB symmetrical OTA with improved CMRR / Centurelli, Francesco; Monsurro, Pietro; Parisi, Gaetano; Tommasino, Pasquale; Trifiletti, Alessandro. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - 65:11(2018), pp. 1504-1508. [10.1109/TCSII.2017.2742240]
A topology of fully differential class-AB symmetrical OTA with improved CMRR
Centurelli, Francesco
;Monsurro, Pietro;Parisi, Gaetano;Tommasino, Pasquale;Trifiletti, Alessandro
2018
Abstract
An improvement of a standard fully differential class-AB symmetrical operational transconductance amplifier (OTA) topology is proposed in this brief to enhance the common-mode behavior. Common-mode behavior could be critical in fully differential class-AB OTAs, where the total current is not fixed and differential to common-mode conversion could therefore be present. A signal proportional to the input commonmode component is generated through a simple low-current auxiliary amplifier and used to modulate a bias voltage, achieving cancellation of the output common-mode component. Simulations in 40-nm CMOS technology show a net improvement of common mode rejection ratio without affecting differential-mode behavior; the increase in area and power consumption is minimal, with a tradeoff between power and settling time. Simulations of a sample-and-hold exploiting the proposed OTA are presented.File | Dimensione | Formato | |
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