In this paper we investigate in detail how the heterostructure concept can be implemented in an interdigitated back contact solar cell, in which both the emitters are formed on the back side of the c-Si wafer by amorphous/crystalline silicon heterostructure, and at the same time the grid-less front surface is passivated by a double layer of amorphous silicon and silicon nitride, which also provides an anti-reflection coating. The entire process, held at temperature below 300 °C, is photolithography-free, using a metallic self-aligned mask to create the interdigitated pattern. An open-circuit voltage of 695 mV has been measured on this device fabricated. The mask-assisted deposition process does not influence the uniformity of the deposited amorphous silicon layers. Several technological aspects that limit the fill factor are considered and discussed
Back Enhanced Heterostructure with Interdigitated Contact-BEHIND- Solar Cell / Tucci, M.; Serenelli, ; L., Salza; Pirozzi, L.; DE CESARE, Giampiero; Caputo, Domenico; Ceccarelli, M.; Martufi, P.; De Iuliis, S.; Geerligs, L.. - STAMPA. - (2008), pp. 1749-1752. (Intervento presentato al convegno CONFERENCE ON OPTOELECTRONIC AND MICROELECTRONIC MATERIALS & DEVICES tenutosi a Sydney, AUSTRALIA nel JUL 28-SEP 01, 2008) [10.1109/COMMAD.2008.4802136].
Back Enhanced Heterostructure with Interdigitated Contact-BEHIND- Solar Cell
DE CESARE, Giampiero;CAPUTO, Domenico;
2008
Abstract
In this paper we investigate in detail how the heterostructure concept can be implemented in an interdigitated back contact solar cell, in which both the emitters are formed on the back side of the c-Si wafer by amorphous/crystalline silicon heterostructure, and at the same time the grid-less front surface is passivated by a double layer of amorphous silicon and silicon nitride, which also provides an anti-reflection coating. The entire process, held at temperature below 300 °C, is photolithography-free, using a metallic self-aligned mask to create the interdigitated pattern. An open-circuit voltage of 695 mV has been measured on this device fabricated. The mask-assisted deposition process does not influence the uniformity of the deposited amorphous silicon layers. Several technological aspects that limit the fill factor are considered and discussedI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
