We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is comparable to O (100) carefully programmed high-end PCs: it turns out to be even better for some selected spin models. We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system. © 2007 Elsevier B.V. All rights reserved.
Simulating spin systems on IANUS, an FPGA-based computer / F., Belletti; M., Cotallo; A., Cruz; L. A., Fernandez; A., Gordillo; Maiorano, Andrea; F., Mantovani; Marinari, Vincenzo; V., Martin Mayor; A., Munoz Sudupe; D., Navarro; S., Perez Gaviro; J. J., Ruiz Lorenzo; S. F., Schifano; D., Sciretti; A., Tarancon; R., Tripiccione; J. L., Velasco. - In: COMPUTER PHYSICS COMMUNICATIONS. - ISSN 0010-4655. - STAMPA. - 178:3(2008), pp. 208-216. [10.1016/j.cpc.2007.09.006]
Simulating spin systems on IANUS, an FPGA-based computer
MAIORANO, Andrea;MARINARI, Vincenzo;
2008
Abstract
We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is comparable to O (100) carefully programmed high-end PCs: it turns out to be even better for some selected spin models. We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system. © 2007 Elsevier B.V. All rights reserved.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
