Increasingly demanding industrial applications require fast and cheap computing tools for real-time control. For example, high performance industrial robotics would benefit from fast and cheap computing, but fast structures are generally expensive and dedicated to particular tasks [ 1,2,3]. Another example which requires fast computing is the control of electrical transients of ac motors, where complex numerical computations must be carried out within times like 1 ms . A recent paper described implementation of a self-tuning controller which uses a digital signal processing chip for rapid calculations . For many control applications there is a natural hierarchical structure so that algorithms devoted to simple tasks are placed at the lowest level (for example, controlling a robot axis or determining the switching time of a static converter), whereas complex tasks are at the high levels, forming a pyramidal control structure which reflects the multilevel structure described by Mesarovic .I n such a structure, tasks are usually repetitive and involve rapid manipulation of data, directly derived from the measurements of sensors, while high-level tasks are done over larger time intervals with more complex algorithms. This paper describes a computing structure taking into account the hierarchical considerations above. The architecture consists of a high level general purpose computer (HOST) and up to eight digital signal processors (DSPs) which can be interfaced with the controlled plant(s). The high-level computer is either a work station or an advanced personal computer with sufficient memory space (RAM and mass memory), equipped with peripherals for implementation of user-friendly interface and with the ability to communicate with other computers, perhaps in a local network. The synchronization and the real-time communications between the HOST and a DSP are implemented by the two memory bank alternatively switched between the HOST and the DSP. A complete transparency and a minimum overhead result for the tasks running on the DSP.
An architecture for high performance control using digital signal processing chips / Battilotti, Stefano; G., Ulivi. - In: IEEE CONTROL SYSTEMS MAGAZINE. - ISSN 0272-1708. - STAMPA. - 10:6(1990), pp. 20-23.
|Titolo:||An architecture for high performance control using digital signal processing chips|
BATTILOTTI, Stefano (Corresponding author)
|Data di pubblicazione:||1990|
|Citazione:||An architecture for high performance control using digital signal processing chips / Battilotti, Stefano; G., Ulivi. - In: IEEE CONTROL SYSTEMS MAGAZINE. - ISSN 0272-1708. - STAMPA. - 10:6(1990), pp. 20-23.|
|Appartiene alla tipologia:||01a Articolo in rivista|