In this paper we investigate in detail how the heterostructure concept can be implemented in an interdigitated back contact solar cell, in which both the emitters are formed on the back side of the c-Si wafer by amorphous/crystalline silicon heterostructure, and at the same time the grid-less front surface is passivated by a double layer of amorphous silicon and silicon nitride, which also provides an anti-reflection coating. The entire process, held at temperature below 300°C, is photolithography-free, using a metallic self-aligned mask to create the interdigitated pattern, and we show that the alignment is feasible. An open-circuit voltage of 687 mV has been measured on a p-type monocrystalline silicon wafer. The mask-assisted deposition process does not influence the uniformity of the deposited amorphous silicon layers. Photocurrent limits factor has been investigated with the aid of one-dimensional modeling and quantum efficiency measurements. On the other hand several technological aspects that limit the fill factor and the short circuit current density still need improvements
Novel scheme of Amorphous/crystalline silicon heterojunction solar cell / M., Tucci; L., Serenelli; E., Salza; S., De Iuliis; L. J., Geerligs; DE CESARE, Giampiero; Caputo, Domenico; M., Ceccarelli. - STAMPA. - (2007), pp. 1600-1603. (Intervento presentato al convegno Proceeding of XXII European Photovoltaic Solar Energy Conference tenutosi a Milano -Italia nel 3-7 set 2007).
Novel scheme of Amorphous/crystalline silicon heterojunction solar cell
DE CESARE, Giampiero;CAPUTO, Domenico;
2007
Abstract
In this paper we investigate in detail how the heterostructure concept can be implemented in an interdigitated back contact solar cell, in which both the emitters are formed on the back side of the c-Si wafer by amorphous/crystalline silicon heterostructure, and at the same time the grid-less front surface is passivated by a double layer of amorphous silicon and silicon nitride, which also provides an anti-reflection coating. The entire process, held at temperature below 300°C, is photolithography-free, using a metallic self-aligned mask to create the interdigitated pattern, and we show that the alignment is feasible. An open-circuit voltage of 687 mV has been measured on a p-type monocrystalline silicon wafer. The mask-assisted deposition process does not influence the uniformity of the deposited amorphous silicon layers. Photocurrent limits factor has been investigated with the aid of one-dimensional modeling and quantum efficiency measurements. On the other hand several technological aspects that limit the fill factor and the short circuit current density still need improvementsI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.