Spin-glasses have become one of the most computing-demanding problems of the last 50 years in Statistical Physics. These extremely slow systems represent a clear example of an easy-to-describe but hard-to-simulate numerical problem. We have developed an FPGAs architecture, called Janus, able to exploit the simplicity of the problem by an extensive parallelization of the computing units. In this work we describe the architecture after motivating the problem. We give the performance figures compared with other more usual architectures. We have obtained a clear advantage in terms of computing power which produced several top results in the field. In addition, we describe the current development of the next generation of the infrastructure: Janus II. © IFAC.
The Janus project: Boosting spin-glass simulations using FPGAs / M., Baity Jesi; R. A., Ba Nos; A., Cruz; L. A., Fernandez; J. M., Gil Narvion; A., Gordillo Guerrero; D. I., Niguez; Maiorano, Andrea; F., Mantovani; Marinari, Vincenzo; V., Martin Mayor; J., Monforte Garcia; A., Mu Noz Sudupe; D., Navarro; Parisi, Giorgio; S., Perez Gaviro; M., Pivanti; RICCI TERSENGHI, Federico; J. J., Ruiz Lorenzo; S. F., Schifano; B., Seoane; A., Tarancon; R., Tripiccione; D., Yllanes. - ELETTRONICO. - 12:PART 1(2013), pp. 227-232. (Intervento presentato al convegno 12th IFAC Conference on Programmable Devices and Embedded Systems, PDeS 2013 tenutosi a Velke Karlovice; Czech Republic nel 25 September 2013 through 27 September 2013) [10.3182/20130925-3-cz-3023.00039].
The Janus project: Boosting spin-glass simulations using FPGAs
MAIORANO, Andrea;MARINARI, Vincenzo;PARISI, Giorgio;RICCI TERSENGHI, Federico;
2013
Abstract
Spin-glasses have become one of the most computing-demanding problems of the last 50 years in Statistical Physics. These extremely slow systems represent a clear example of an easy-to-describe but hard-to-simulate numerical problem. We have developed an FPGAs architecture, called Janus, able to exploit the simplicity of the problem by an extensive parallelization of the computing units. In this work we describe the architecture after motivating the problem. We give the performance figures compared with other more usual architectures. We have obtained a clear advantage in terms of computing power which produced several top results in the field. In addition, we describe the current development of the next generation of the infrastructure: Janus II. © IFAC.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
