Loss analysis of low-voltage TLNPC step-up converters

Power losses in high-efficiency dc-dc step up converters based on the synchronous Three Levels Neutral Point Clamped (TLNPC) configuration were investigated. TLNPC converters benefit from the reduced stress on components and from the non insulated stacked-boost output stage in order to provide reduced power losses and large voltage gains. Several prototypes with increasing efficiency were produced and tested: voltage gains larger than 20´ were achieved by means of hard-switched prototypes with composite switches consisting of both low-Rds(ON) and high-speed MOSFETs. At lower voltage gains conversion efficiencies exceeding 98% were demonstrated. A thorough loss analysis is reported, extended to subtle power dissipation processes, which in high efficiency converters grow in relevance after weakening of the major loss mechanisms. The related model is proven capable to accurately predict circuit performance in a wide range of operating conditions.