This work presents an analysis of power efficiency in microprocessor architectures targeting wide-range digital signal processing (DSP) applications. We defined a circuit level power estimation technique based on the integration of traditional analytical power models so as to account for both block-internal and interconnects-dependent dissipation and we extended it to provide applicability to specific DSP-related structures. We applied the modeling approach to several architecture schemes and demonstrated that a relatively novel solution, namely the transfer triggered architecture, can be the most power-efficient scheme in DSP applications.
Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique / Olivieri, Mauro; M., Scarana; Smorfa, Simone. - (2005), pp. 5266-5269. (Intervento presentato al convegno IEEE International Symposium on Circuits and Systems (ISCAS) tenutosi a Kobe, JAPAN nel MAY 23-26, 2005) [10.1109/iscas.2005.1465823].
Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique
OLIVIERI, Mauro;SMORFA, SIMONE
2005
Abstract
This work presents an analysis of power efficiency in microprocessor architectures targeting wide-range digital signal processing (DSP) applications. We defined a circuit level power estimation technique based on the integration of traditional analytical power models so as to account for both block-internal and interconnects-dependent dissipation and we extended it to provide applicability to specific DSP-related structures. We applied the modeling approach to several architecture schemes and demonstrated that a relatively novel solution, namely the transfer triggered architecture, can be the most power-efficient scheme in DSP applications.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
