Fast closed-loop-power-control (CLPC) plays a key role in direct-sequence (DS) code division multiple access (CDMA) systems, aiming at achieving acceptable carrier-to-interference (C/I) ratios in all active links. Assuming a terrestrial mobile access, where the round-trip delay may be smaller than the channel time-coherence, fast CLPC can compensate for fading and reduce the error burstiness, as well. This paper provides analytical expressions for the bit error probability given: the CLPC algorithm specified in terms of loop delay and updating rate, the propagation power-delay-profile and the terminal speed. A binary PSK DS spread spectrum radio interface, with rake processing of multipath or diversity, is considered. Our link-level analysis, being conditioned to a specified average value of CII, is focused on the inverse update algorithm, which is aimed at keeping the received power at a constant level. Applications of the derived method, aimed at getting insight about CLPC performance in 3rd generation radio interfaces, is also provided and discussed.
Error probability analysis for CDMA systems with closed-loop power control / S., De Fina; Lombardo, Pierfrancesco. - In: IEEE TRANSACTIONS ON COMMUNICATIONS. - ISSN 0090-6778. - 49:10(2001), pp. 1801-1811. [10.1109/26.957402]
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|Titolo:||Error probability analysis for CDMA systems with closed-loop power control|
|Data di pubblicazione:||2001|
|Citazione:||Error probability analysis for CDMA systems with closed-loop power control / S., De Fina; Lombardo, Pierfrancesco. - In: IEEE TRANSACTIONS ON COMMUNICATIONS. - ISSN 0090-6778. - 49:10(2001), pp. 1801-1811. [10.1109/26.957402]|
|Appartiene alla tipologia:||01a Articolo in rivista|