The gamma cameras built on a LaBr3 crystal and Hamamatsu H8500 that are being developed have a number of channel that can vary from 64 to 256 depending on the number of PSPMTs that are used and, due to the gain differences, channels have to be acquired and corrected individually. In this context, the readout electronics has to be able to acquire and possibly to make computations on a high number of channels at a rate of kiloevents. A possible solution is the use of an FPGA programmed to collect the data and, in parallel, make a preliminary analysis. The high number of pins available on a modern FPGA allows to acquire and to manage all the data coming from the ADCs, driving the control signals and acquiring the data from several device at the same time. The possibility, even on average grade FPGAs, of having clock rate in the 100 MHz range, makes it feasible to make preliminary energy discrimination in order not to overload the communication channel with the control PC that, due to the high number of data, can became the real bottleneck of system. ©2009 IEEE.
FPGA based readout electronics for multi anode PSPMT / A., Fabbri; F., De Notaristefani; V. O., Cencelli; F., Petulla; E., D'Abramo; Pani, Roberto; G., Moschini; F., Navarria. - STAMPA. - (2009), pp. 357-359. (Intervento presentato al convegno 2009 IEEE Nuclear Science Symposium Conference Record, NSS/MIC 2009 tenutosi a Orlando, FL nel 25 October 2009 through 31 October 2009) [10.1109/nssmic.2009.5401699].
FPGA based readout electronics for multi anode PSPMT
PANI, Roberto;
2009
Abstract
The gamma cameras built on a LaBr3 crystal and Hamamatsu H8500 that are being developed have a number of channel that can vary from 64 to 256 depending on the number of PSPMTs that are used and, due to the gain differences, channels have to be acquired and corrected individually. In this context, the readout electronics has to be able to acquire and possibly to make computations on a high number of channels at a rate of kiloevents. A possible solution is the use of an FPGA programmed to collect the data and, in parallel, make a preliminary analysis. The high number of pins available on a modern FPGA allows to acquire and to manage all the data coming from the ADCs, driving the control signals and acquiring the data from several device at the same time. The possibility, even on average grade FPGAs, of having clock rate in the 100 MHz range, makes it feasible to make preliminary energy discrimination in order not to overload the communication channel with the control PC that, due to the high number of data, can became the real bottleneck of system. ©2009 IEEE.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
