An important problem in real-time DSP (digital signal-processing) systems with highly integrated components is the capability of automatic error detection and correction. The use of residue number arithmetic allows error detection and correction because of its unweighted nature. A single-error-correction procedure is proposed which is based on the use of redundant residue number systems (RRNS) and the base extension operation. The proposed method uses a small decision table and works in parallel mode; therefore it is suitable for high-speed VLSI circuit realization. A parallel architecture which realizes the method is also introduced
Parallel error correction algorithm in RNS VLSI digital circuits / DI CLAUDIO, Elio; Orlandi, Gianni; F., Piazza. - STAMPA. - 3:(1988), pp. 1738-1741. (Intervento presentato al convegno 1988 International Conference on Acoustics, Speech, and Signal Processing. ICASSP-88 tenutosi a New York, NY, USA nel 11-14 Apr 1988) [10.1109/ICASSP.1988.196953].
Parallel error correction algorithm in RNS VLSI digital circuits
DI CLAUDIO, Elio;ORLANDI, Gianni;
1988
Abstract
An important problem in real-time DSP (digital signal-processing) systems with highly integrated components is the capability of automatic error detection and correction. The use of residue number arithmetic allows error detection and correction because of its unweighted nature. A single-error-correction procedure is proposed which is based on the use of redundant residue number systems (RRNS) and the base extension operation. The proposed method uses a small decision table and works in parallel mode; therefore it is suitable for high-speed VLSI circuit realization. A parallel architecture which realizes the method is also introducedI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
