Several DSP (digital signal processor) structures based on residual number systems (RNSs) have been proposed in the technical literature. Most of them use a lookup-table approach, which consumes space on the chip and lacks flexibility and reprogrammability. Small binary structures based on pseudoresidue odd-moduli RNS are presented and shown to be highly efficient in terms of speed, area, and reprogrammability, especially when large structures are to be built. The proposed method allows easy estimation of the overall complexity of an RNS algorithm with respect to other possible implementations. A mixed radix reconstruction cell and two examples of FIR (finite impulse response) filter structures are developed using this approach. These examples demonstrate all the advantages of the proposed scheme when used with the highly concurrent and repetitive architectures typical of VLSI/VHSIC design
A fast binary arithmetic implementation of RNS DSP processors / DI CLAUDIO, Elio; Orlandi, Gianni; F., Piazza. - STAMPA. - 3:(1990), pp. 2120-2123. (Intervento presentato al convegno IEEE International Symposium on Circuits and Systems 1990 tenutosi a New Orleans, LA , USA nel 01-03 May 1990) [10.1109/ISCAS.1990.112228].
A fast binary arithmetic implementation of RNS DSP processors
DI CLAUDIO, Elio;ORLANDI, Gianni;
1990
Abstract
Several DSP (digital signal processor) structures based on residual number systems (RNSs) have been proposed in the technical literature. Most of them use a lookup-table approach, which consumes space on the chip and lacks flexibility and reprogrammability. Small binary structures based on pseudoresidue odd-moduli RNS are presented and shown to be highly efficient in terms of speed, area, and reprogrammability, especially when large structures are to be built. The proposed method allows easy estimation of the overall complexity of an RNS algorithm with respect to other possible implementations. A mixed radix reconstruction cell and two examples of FIR (finite impulse response) filter structures are developed using this approach. These examples demonstrate all the advantages of the proposed scheme when used with the highly concurrent and repetitive architectures typical of VLSI/VHSIC designI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
