Operation of a S/C power system based on the SMP technique for Maximum Power Point Tracking management is the subject of the present work. 12Improvements both in transient behaviour and EMC are reported and experimental results are analysed with reference to specific design solutions. Particular design techniques are then presented, specifically developed to avoid that the increased circuit complexity could negatively affect the system reliability, especially in the cases where Commercial Off The Shelf components are used. Basically, the circuits for fundamental operation, designed on the basis of classical and very reliable schemes, are separated from those dedicated to the SMP control, based on digital integrated circuits, with an higher failure rate. Then, the interfaces between the two blocks are designed so that the SMP control circuit can only affect (positively) the system operation when it is correctly operating, while its interactions with the basic circuit are blocked if errors are detected. ©2009 IEEE.
Reliable design for MPPT management through the SMP technique / Schirone, Luigi; Macellari, Michele; Schiaratura, A.. - ELETTRONICO. - (2009), pp. 1-9. (Intervento presentato al convegno 2009 IEEE Aerospace Conference tenutosi a Big Sky; United States nel 7-14 marzo 2009,) [10.1109/AERO.2009.4839521].
Reliable design for MPPT management through the SMP technique
SCHIRONE, Luigi;MACELLARI, MICHELE;
2009
Abstract
Operation of a S/C power system based on the SMP technique for Maximum Power Point Tracking management is the subject of the present work. 12Improvements both in transient behaviour and EMC are reported and experimental results are analysed with reference to specific design solutions. Particular design techniques are then presented, specifically developed to avoid that the increased circuit complexity could negatively affect the system reliability, especially in the cases where Commercial Off The Shelf components are used. Basically, the circuits for fundamental operation, designed on the basis of classical and very reliable schemes, are separated from those dedicated to the SMP control, based on digital integrated circuits, with an higher failure rate. Then, the interfaces between the two blocks are designed so that the SMP control circuit can only affect (positively) the system operation when it is correctly operating, while its interactions with the basic circuit are blocked if errors are detected. ©2009 IEEE.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
