This work presents a novel approach to optimize digital integrated circuits yield referring to speed, dynamic power and leakage power constraints. The method is based on process parameter estimation circuits and active control of body bias performed by an on-chip digital controller. The associated design flow allows us to quantitatively predict the impact of the method on the expected yield in a specific design.We present the architecture scheme, the theoretical foundation, the estimation circuits used, and two application case studies, referring to an industrial 0.13- m CMOS process data. The approach results to be remarkably effective at high operating temperature. In the presented case study, initial yields below 14% are improved to 86% by using a single controller and a single set of estimation circuits per die.

A novel yield optimisation technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control / Olivieri, Mauro; Scotti, Giuseppe; Trifiletti, Alessandro. - In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. - ISSN 1063-8210. - 13:(2005), pp. 630-638. [10.1109/TVLSI.2005.844290]

A novel yield optimisation technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control

OLIVIERI, Mauro;SCOTTI, Giuseppe;TRIFILETTI, Alessandro
2005

Abstract

This work presents a novel approach to optimize digital integrated circuits yield referring to speed, dynamic power and leakage power constraints. The method is based on process parameter estimation circuits and active control of body bias performed by an on-chip digital controller. The associated design flow allows us to quantitatively predict the impact of the method on the expected yield in a specific design.We present the architecture scheme, the theoretical foundation, the estimation circuits used, and two application case studies, referring to an industrial 0.13- m CMOS process data. The approach results to be remarkably effective at high operating temperature. In the presented case study, initial yields below 14% are improved to 86% by using a single controller and a single set of estimation circuits per die.
2005
01 Pubblicazione su rivista::01a Articolo in rivista
A novel yield optimisation technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control / Olivieri, Mauro; Scotti, Giuseppe; Trifiletti, Alessandro. - In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. - ISSN 1063-8210. - 13:(2005), pp. 630-638. [10.1109/TVLSI.2005.844290]
File allegati a questo prodotto
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/241279
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo

Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 32
  • ???jsp.display-item.citation.isi??? 27
social impact