We describe continuous time, rail to rail, gain enhanced voltage amplifiers with a gain error which is almost insensitive to mismatch of active devices. Though the proposed approach is general, as a preliminary test we have designed a voltage amplifier in a standard 0.35 mum CMOS process; Montecarlo and AC simulations demonstrate a significant gain enhancement, its robustness against spread of process parameters and a small output resistance.

Mismatch tolerant, continuous time, rail to rail, gain enhanced cmos amplifiers / M., Cianella; A., Damico; C., Falconi; Scotti, Giuseppe; Trifiletti, Alessandro. - (2007), pp. 1-4. (Intervento presentato al convegno 2007 18th European Conference on Circuit Theory and Design tenutosi a Seville; Spain).

Mismatch tolerant, continuous time, rail to rail, gain enhanced cmos amplifiers

SCOTTI, Giuseppe;TRIFILETTI, Alessandro
2007

Abstract

We describe continuous time, rail to rail, gain enhanced voltage amplifiers with a gain error which is almost insensitive to mismatch of active devices. Though the proposed approach is general, as a preliminary test we have designed a voltage amplifier in a standard 0.35 mum CMOS process; Montecarlo and AC simulations demonstrate a significant gain enhancement, its robustness against spread of process parameters and a small output resistance.
2007
2007 18th European Conference on Circuit Theory and Design
gain enhancement low voltage
04 Pubblicazione in atti di convegno::04b Atto di convegno in volume
Mismatch tolerant, continuous time, rail to rail, gain enhanced cmos amplifiers / M., Cianella; A., Damico; C., Falconi; Scotti, Giuseppe; Trifiletti, Alessandro. - (2007), pp. 1-4. (Intervento presentato al convegno 2007 18th European Conference on Circuit Theory and Design tenutosi a Seville; Spain).
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/219316
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