In this paper we analyze a satellite communication system including a Processing Satellite (PS) performing circuit and packet switching. The switching scheme is based upon the separation of the incoming traffic in two components: isochronous (V, voice and video) and non-isochronous (D, data). These two components are simultaneously supported by a TDMA protocol. The V traffic burstiness can be used to increase significantly the overall system throughput; also, a potential statistical gain can be reaped by packet switching the D traffic. The system analyzed succeeds in exploiting both the above features. We model analytically the system at hand, by using sophisticated queueing models, that allow a very accurate performance evaluation and an easy dimensioning of the data buffers. The proposed model is validated with simulation results produced with a computer model of the whole system. Possible solutions for a congestion control scheme are also presented.
Modelling and dimensioning of an integrated circuit and packet switching scheme on-board a processing satellite / Baiocchi, Andrea; N., BLÉFARI MELAZZI; Listanti, Marco; C., Soprano. - STAMPA. - 2:(1996), pp. 936-941. (Intervento presentato al convegno International Conference on Communications 1996 tenutosi a Dallas, TX, USA nel June 1996) [10.1109/ICC.1996.541349].
Modelling and dimensioning of an integrated circuit and packet switching scheme on-board a processing satellite
BAIOCCHI, Andrea;LISTANTI, Marco;
1996
Abstract
In this paper we analyze a satellite communication system including a Processing Satellite (PS) performing circuit and packet switching. The switching scheme is based upon the separation of the incoming traffic in two components: isochronous (V, voice and video) and non-isochronous (D, data). These two components are simultaneously supported by a TDMA protocol. The V traffic burstiness can be used to increase significantly the overall system throughput; also, a potential statistical gain can be reaped by packet switching the D traffic. The system analyzed succeeds in exploiting both the above features. We model analytically the system at hand, by using sophisticated queueing models, that allow a very accurate performance evaluation and an easy dimensioning of the data buffers. The proposed model is validated with simulation results produced with a computer model of the whole system. Possible solutions for a congestion control scheme are also presented.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.