A Novel ultra-low-voltage pseudo-dynamic voltage comparator based on OAI standard-cells

In this paper, a novel Pseudo-Dynamic Voltage Comparator (PDVC), based on OAI (Or-And-Invert) standard-cells, with Non-Rail-to-Rail input common-mode range (ICMR) is presented. The topology exploits OAI gates to reduce the clock-to-output delay and Power-Delay-Product with respect to the other conventional Dynamic Voltage Comparators (DVCs) in literature, and, its operating principle is described in detail at transistor level. The overall performance of the circuit is assessed, referring to a 45 nm CMOS technology, considering three different supply voltages: 0.6 V, 0.3 V and 0.15 V, along the entire input common mode range. The results demonstrate the strong advantages of the proposed PDVC, in terms of speed and Power-Delay-Product, with respect to the other conventional Non-Rail-to-Rail DVCs in literature, especially with hardly scaled supply voltages down to 0.15 V.