RED-SEA is a H2020 EuroHPC project, whose main objective is to prepare a new-generation European Interconnect, capable of powering the EU Exascale systems to come, through an economically viable and technologically efficient interconnect, leveraging European interconnect technology (BXI) associated with standard and mature technology (Ethernet), previous EU-funded initiatives, as well as open standards and compatible APIs. To achieve this objective, the RED-SEA project is being carried out around four key pillars: (i) network architecture and workload requirements-interconnects co-design – aiming at optimizing the fit with the other EuroHPC projects and with the EPI processors; (ii) development of a high-performance, low-latency, seamless bridge with Ethernet; (iii) efficient network resource management, including congestion and Quality-of-Service; and (iv) end-to-end functions implemented at the network edges. This paper presents key achievements and results at the midterm of the project for each key pillar in the way to reach the final project objective. In this regard we can highlight: (i) The definition of the network requirements and architecture as well as a list of benchmarks and applications; (ii) In addition to initially planned IPs progress, BXI3 architecture has evolved to support natively Ethernet at low level, resulting in reduced complexity, with advantages in terms of cost optimization, and power consumption; (iii) The congestion characterization of target applications and proposals to reduce this congestion by the optimization of collective communication primitives, injection throttling and adaptive routing; and (iv) the low-latency high-message rate endpoint functions and their connection with new open technologies.
RED-SEA Project: Towards a new-generation European interconnect / Gomez, Maria Engracia; Sahuquillo, Julio; Biagioni, Andrea; Chrysos, Nikos; Berton, Damien; Frezza, Ottorino; Lo Cicero, Francesca; Lonardo, Alessandro; Martinelli, Michele; Paolucci, Pier Stanislao; Pastorelli, Elena; Simula, Francesco; Turisini, Matteo; Vicini, Piero; Ammendola, Roberto; Chiarini, Carlotta; De Luca, Chiara; Capuani, Fabrizio; Castelló, Adrián; Duro, Jose; Stabile, Eugenio; Quintana, Enrique; Bernier-Bruna, Pascale; Chen, Claire; Lagadec, Pierre-Axel; Pichon, Gregoire; Walter, Etienne; Katevenis, Manolis; Bartzis, Sokratis; Mousouros, Orestis; Xirouchakis, Pantelis; Mageiropoulos, Vangelis; Gianioudis, Michalis; Loukas, Harisis; Ioannou, Aggelos; Kallimanis, Nikos; De La Rosa, Miguel Sanchez; Gomez-Lopez, Gabriel; Alfaro-Cortés, Francisco; Sahuquillo, Jesus Escudero; Garcia, Pedro Javier; Quiles, Francisco J.; Sanchez, Jose L.; De Gassowski, Gaetan; Hautreaux, Matthieu; Mathieu, Stephane; Moreau, Gilles; Perache, Marc; Taboada, Hugo; Hoefler, Torsten; Schneider, Timo; Barnaba, Matteo; Brandino, Giuseppe Piero; De Giorgi, Francesco; Poggi, Matteo; Mavroidis, Iakovos; Papaefstathiou, Yannis; Tampouratzis, Nikolaos; Kalisch, Benjamin; Krackhardt, Ulrich; Nuessle, Mondrian; Frings, Wolfang; Gottwald, Dominik; Guimaraes, Felime; Holicki, Max; Marx, Volker; Muller, Yannik; Clauss, Carsten; Falter, Hugo; Huang, Xu; Barillao, Jennifer Lopez; Moschny, Thomas; Pickartz, Simon. - In: MICROPROCESSORS AND MICROSYSTEMS. - ISSN 0141-9331. - 110:(2024). [10.1016/j.micpro.2024.105102]
RED-SEA Project: Towards a new-generation European interconnect
Lonardo, Alessandro;Martinelli, Michele;Pastorelli, Elena;Simula, Francesco;Vicini, Piero;Chiarini, Carlotta;Capuani, Fabrizio;Poggi, Matteo;Huang, Xu;
2024
Abstract
RED-SEA is a H2020 EuroHPC project, whose main objective is to prepare a new-generation European Interconnect, capable of powering the EU Exascale systems to come, through an economically viable and technologically efficient interconnect, leveraging European interconnect technology (BXI) associated with standard and mature technology (Ethernet), previous EU-funded initiatives, as well as open standards and compatible APIs. To achieve this objective, the RED-SEA project is being carried out around four key pillars: (i) network architecture and workload requirements-interconnects co-design – aiming at optimizing the fit with the other EuroHPC projects and with the EPI processors; (ii) development of a high-performance, low-latency, seamless bridge with Ethernet; (iii) efficient network resource management, including congestion and Quality-of-Service; and (iv) end-to-end functions implemented at the network edges. This paper presents key achievements and results at the midterm of the project for each key pillar in the way to reach the final project objective. In this regard we can highlight: (i) The definition of the network requirements and architecture as well as a list of benchmarks and applications; (ii) In addition to initially planned IPs progress, BXI3 architecture has evolved to support natively Ethernet at low level, resulting in reduced complexity, with advantages in terms of cost optimization, and power consumption; (iii) The congestion characterization of target applications and proposals to reduce this congestion by the optimization of collective communication primitives, injection throttling and adaptive routing; and (iv) the low-latency high-message rate endpoint functions and their connection with new open technologies.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
