Flight-Safe Inference: SVD-Compressed LSTM Acceleration for Real-Time UAV Engine Monitoring Using Custom FPGA Hardware Architecture

Predictive maintenance (PdM) is a proactive strategy that enhances safety, minimizes unplanned downtime, and optimizes operational costs by forecasting equipment failures before they occur. This study presents a novel Field Programmable Gate Array (FPGA)-accelerated predictive maintenance framework for UAV engines using a Singular Value Decomposition (SVD)-optimized Long Short-Term Memory (LSTM) model. The model performs binary classification to predict the likelihood of imminent engine failure by processing normalized multi-sensor data, including temperature, pressure, and vibration measurements. To enable real-time deployment on resource-constrained UAV platforms, the LSTM’s weight matrices are compressed using Singular Value Decomposition (SVD), significantly reducing computational complexity while preserving predictive accuracy. The compressed model is executed on a Xilinx ZCU-104 FPGA and uses a pipelined, AXI-based hardware accelerator with efficient memory mapping and parallelized gate calculations tailored for low-power onboard systems. Unlike prior works, this study uniquely integrates a tailored SVD compression strategy with a custom hardware accelerator co-designed for real-time, flight-safe inference in UAV systems. Experimental results demonstrate a 98% classification accuracy, a 24% reduction in latency, and substantial FPGA resource savings—specifically, a 26% decrease in BRAM usage and a 37% reduction in DSP consumption—compared to the 32-bit floating-point SVD-compressed FPGA implementation, not CPU or GPU. These findings confirm the proposed system as an efficient and scalable solution for real-time UAV engine health monitoring, thereby enhancing in-flight safety through timely fault prediction and enabling autonomous engine monitoring without reliance on ground communication.