In this paper, a NOR2 standard-cell-based dynamic comparator providing rail-to-rail input common mode range (ICMR) is presented, together with a novel standard-cell oriented design methodology. The proposed topology provides better speed performance and lower power-delay-product than the previously presented standard-cell-based dynamic comparators with rail-to-rail ICMR features. The NOR2 topology, which is also better than the complementary NAND2-based topology previously presented by the authors, is even able to guarantee improvements in the order of 8× –16× higher speed and 7× lower PDP, with respect to the other rail-to-rail ICMR standard-cell-based topologies in the literature. Concerning the standard-cell oriented design methodology, it is focused on the impact of the cell’s strength, which is the only free parameter, on delay, power consumption, ICMR and offset. The circuit performances are demonstrated for supply voltages equal to 600 mV, 300 mV and 150 mV, considering a 45 nm CMOS technology.

Design of ultra-low-power rail-to-rail input common mode range standard-cell-based comparators / Manno, A.; Scotti, G.; Palumbo, G.. - In: JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS. - ISSN 2079-9268. - 15:1(2025). [10.3390/jlpea15010014]

Design of ultra-low-power rail-to-rail input common mode range standard-cell-based comparators

Scotti G.;
2025

Abstract

In this paper, a NOR2 standard-cell-based dynamic comparator providing rail-to-rail input common mode range (ICMR) is presented, together with a novel standard-cell oriented design methodology. The proposed topology provides better speed performance and lower power-delay-product than the previously presented standard-cell-based dynamic comparators with rail-to-rail ICMR features. The NOR2 topology, which is also better than the complementary NAND2-based topology previously presented by the authors, is even able to guarantee improvements in the order of 8× –16× higher speed and 7× lower PDP, with respect to the other rail-to-rail ICMR standard-cell-based topologies in the literature. Concerning the standard-cell oriented design methodology, it is focused on the impact of the cell’s strength, which is the only free parameter, on delay, power consumption, ICMR and offset. The circuit performances are demonstrated for supply voltages equal to 600 mV, 300 mV and 150 mV, considering a 45 nm CMOS technology.
2025
CMOS; comparators; dynamic comparator; IoT; logic gates; standard cell; ultra-low power; ultra-low voltage
01 Pubblicazione su rivista::01a Articolo in rivista
Design of ultra-low-power rail-to-rail input common mode range standard-cell-based comparators / Manno, A.; Scotti, G.; Palumbo, G.. - In: JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS. - ISSN 2079-9268. - 15:1(2025). [10.3390/jlpea15010014]
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/1737863
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