In this paper, we present Faust, a pipelined FPU for vector processing-capable RISC-V core developed within the European Processor Initiative (EPI) project. Faust is based on the open-source multi-format floating-point architecture FPnew that was extended and redesigned to support the RISC-V Vector extension specification (RVV) 1.0 and the most recent IEEE 754-2019 FP standard. Faust is extensively tested, mature and configurable, enabling ease of integration, as will be demonstrated in the paper. Faust can produce two binary32 operations or one binary64 operation per clock cycle. We have also developed FPU-V, an update of the SoftFloat-based reference model as a critical part of the UVM-based universal and extensible FPU verification environment. Faust was integrated and taped out as part of Vitruvius, a RISC-V Vector Processing unit of the EPAC1.0, the first EPI Accelerator Test Chip in GlobalFoundries 22FDX technology, and was shown fully operational at a target frequency of 1 GHz.

FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit / Kovac, M.; Dragic, L.; Malnar, B.; Minervini, F.; Palomar, O.; Rojas, C.; Olivieri, M.; Knezovic, J.; Kovac, M.. - In: MICROPROCESSORS AND MICROSYSTEMS. - ISSN 0141-9331. - 97:(2023), pp. 1-9. [10.1016/j.micpro.2023.104762]

FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit

Olivieri M.;
2023

Abstract

In this paper, we present Faust, a pipelined FPU for vector processing-capable RISC-V core developed within the European Processor Initiative (EPI) project. Faust is based on the open-source multi-format floating-point architecture FPnew that was extended and redesigned to support the RISC-V Vector extension specification (RVV) 1.0 and the most recent IEEE 754-2019 FP standard. Faust is extensively tested, mature and configurable, enabling ease of integration, as will be demonstrated in the paper. Faust can produce two binary32 operations or one binary64 operation per clock cycle. We have also developed FPU-V, an update of the SoftFloat-based reference model as a critical part of the UVM-based universal and extensible FPU verification environment. Faust was integrated and taped out as part of Vitruvius, a RISC-V Vector Processing unit of the EPAC1.0, the first EPI Accelerator Test Chip in GlobalFoundries 22FDX technology, and was shown fully operational at a target frequency of 1 GHz.
2023
chip; European processor initiative; exascale computing; Faust; FPU; FPU-V; HPC; RISC-V; vector processor
01 Pubblicazione su rivista::01a Articolo in rivista
FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit / Kovac, M.; Dragic, L.; Malnar, B.; Minervini, F.; Palomar, O.; Rojas, C.; Olivieri, M.; Knezovic, J.; Kovac, M.. - In: MICROPROCESSORS AND MICROSYSTEMS. - ISSN 0141-9331. - 97:(2023), pp. 1-9. [10.1016/j.micpro.2023.104762]
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/1699648
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