FPGA Implementation of a Parallel DDS for Wide-Band Applications

In this paper, the authors propose a parallel Digital Direct Synthesis (DDS) suitable for digital ultra wide-band systems. The proposed architecture offers the possibility to generate sine and/or cosine waves with a user-defined level of parallelism without the necessity to increase the clock frequency. It has been designed in SIMULINK coded in VHDL at RTL level and finally implemented on a Xilinx FPGA. Synthesis and place & route have been performed using the XILINX VIVADO toolchain. Results are provided in terms of hardware resources, speed, and power consumption considering a level of parallelism equal to 4. Implementation results show a low area complexity and very reduced power consumption that coupled with the flexibility in terms of parallelism level make this DDS useful in ultrawideband low-power systems. In particular, the DDS is characterized by an energy per operation of about 91 pJ. The reduced hardware complexity allows its implementation on low-cost FPGA.