This paper presents a novel implementation of a digital-based Operational Transconductance Amplifier (OTA) which has been recently introduced in the technical literature as a fully digital alternative to the conventional differential pair to implement low voltage analog amplifiers and comparators. The proposed implementation does not make use of resistors, floating gate resistors nor C-Muller elements and is made up of only digital gates usually available in the standard cell libraries. The resulting analog circuit schematic can be described using structural VHDL or Verilog languages and is suitable to be integrated in an automatic synthesis and place and route flow for digital circuits. The proposed digital-based amplifier has been implemented in a commercial 130 nm CMOS process by using an automatic place and route flow for layout generation starting from the Verilog netlist. Post layout simulations are presented to show the performance of the proposed circuit and compare it against the state of the art.

A novel standard-cell-based implementation of the digital ota suitable for automatic place and route / Palumbo, Gaetano; Scotti, Giuseppe. - In: JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS. - ISSN 2079-9268. - 11:4(2021), pp. 1-10. [10.3390/jlpea11040042]

A novel standard-cell-based implementation of the digital ota suitable for automatic place and route

Giuseppe Scotti
2021

Abstract

This paper presents a novel implementation of a digital-based Operational Transconductance Amplifier (OTA) which has been recently introduced in the technical literature as a fully digital alternative to the conventional differential pair to implement low voltage analog amplifiers and comparators. The proposed implementation does not make use of resistors, floating gate resistors nor C-Muller elements and is made up of only digital gates usually available in the standard cell libraries. The resulting analog circuit schematic can be described using structural VHDL or Verilog languages and is suitable to be integrated in an automatic synthesis and place and route flow for digital circuits. The proposed digital-based amplifier has been implemented in a commercial 130 nm CMOS process by using an automatic place and route flow for layout generation starting from the Verilog netlist. Post layout simulations are presented to show the performance of the proposed circuit and compare it against the state of the art.
2021
automatic place and route; fully digital; low power; low voltage; OTA; standard cell
01 Pubblicazione su rivista::01a Articolo in rivista
A novel standard-cell-based implementation of the digital ota suitable for automatic place and route / Palumbo, Gaetano; Scotti, Giuseppe. - In: JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS. - ISSN 2079-9268. - 11:4(2021), pp. 1-10. [10.3390/jlpea11040042]
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/1614996
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