Two novel architectures for 4-channel mixing/filtering/processing digitizers

Two architectures of 4-channel mixing-filtering-processing (MFP) digitizers are presented and compared. Both architectures use four analogue-to-digital converters (ADCs), but differ in terms of layout, and are named parallel and hierarchical, respectively. The hierarchical architecture is entirely novel, while the parallel one is at present only envisaged in patent documents. For both architectures, a suitable analytical model, used to determine the effects of several error sources, is provided. Also, digital signal processing techniques, which combine the digitized streams produced by the four ADCs to compensate the errors, are illustrated for both architectures. The computational cost of these techniques, implemented by means of poly-phase filters, is discussed, and their capability of attaining real time performance highlighted. The results of behavioral simulations carried out to assess the performance of the two 4-channel MFP architectures are finally shown.