In this paper we present the Standard Cell Delay-based Dual-rail Pre-charge Logic (SC-DDPL), a novel logic style which is able to counteract Power Analysis Attacks (PAAs) also in the presence of capacitive mismatch at the output of dual-rail gates. The SC-DDPL is based on a standard-cell design flow and it is suitable to be implemented on ASICs or FPGAs without any routing constraint on differential lines, supporting the Time Enclosed Logic protocol along with a DPL structure. The security provided by SC-DDPL has been firstly investigated in simulation on some basic logic gates, designed adopting a commercial 40nm CMOS technology. Simulated experiments have highlighted the capability of SC-DDPL gates to guarantee a high-level of security also in presence of extreme capacitive mismatch, exhibiting strongly reduced NED/NSD metrics, as well as a reduction of the FED, compared to a reference RTZ-based WDDL implementation. In order to compare the proposed logic against other state-of-the-art countermeasures we have implemented a 4bit PRESENT crypto-core adopting several logic styles, evaluating different security metrics on a 65nm Intel Cyclone-IV FPGA. Experimental results have confirmed that the SC-DDPL outperforms other gate-level countermeasures in terms of security metrics with a reasonable area and power consumption overhead.

SC-DDPL. A novel standard-cell based approach for counteracting power analysis attacks in the presence of unbalanced routing / Bellizia, D.; Bongiovanni, S.; Olivieri, M.; Scotti, G.. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS. - ISSN 1549-8328. - 67:7(2020), pp. 2317-2330. [10.1109/TCSI.2020.2979831]

SC-DDPL. A novel standard-cell based approach for counteracting power analysis attacks in the presence of unbalanced routing

Bellizia D.
;
Olivieri M.;Scotti G.
2020

Abstract

In this paper we present the Standard Cell Delay-based Dual-rail Pre-charge Logic (SC-DDPL), a novel logic style which is able to counteract Power Analysis Attacks (PAAs) also in the presence of capacitive mismatch at the output of dual-rail gates. The SC-DDPL is based on a standard-cell design flow and it is suitable to be implemented on ASICs or FPGAs without any routing constraint on differential lines, supporting the Time Enclosed Logic protocol along with a DPL structure. The security provided by SC-DDPL has been firstly investigated in simulation on some basic logic gates, designed adopting a commercial 40nm CMOS technology. Simulated experiments have highlighted the capability of SC-DDPL gates to guarantee a high-level of security also in presence of extreme capacitive mismatch, exhibiting strongly reduced NED/NSD metrics, as well as a reduction of the FED, compared to a reference RTZ-based WDDL implementation. In order to compare the proposed logic against other state-of-the-art countermeasures we have implemented a 4bit PRESENT crypto-core adopting several logic styles, evaluating different security metrics on a 65nm Intel Cyclone-IV FPGA. Experimental results have confirmed that the SC-DDPL outperforms other gate-level countermeasures in terms of security metrics with a reasonable area and power consumption overhead.
2020
ASIC; CMOS; cryptography; DDPL; FPGA; power analysis attack; security; side channel attack; TEL; WDDL
01 Pubblicazione su rivista::01a Articolo in rivista
SC-DDPL. A novel standard-cell based approach for counteracting power analysis attacks in the presence of unbalanced routing / Bellizia, D.; Bongiovanni, S.; Olivieri, M.; Scotti, G.. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS. - ISSN 1549-8328. - 67:7(2020), pp. 2317-2330. [10.1109/TCSI.2020.2979831]
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/1532330
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