Error correction codes (ECCs) are commonly used to protect memories against errors. Among ECCs, orthogonal latin squares (OLS) codes have gained renewed interest for memory protection due to their modularity and the simplicity of the decoding algorithm that enables low delay implementations. An important issue is that when ECCs are used, the encoder and decoder circuits can also suffer errors. In this brief, a concurrent error detection technique for OLS codes encoders and syndrome computation is proposed and evaluated. The proposed method uses the properties of OLS codes to efficiently implement a parity prediction scheme that detects all errors that affect a single circuit node. © 1993-2012 IEEE.

Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation / Reviriego, P; Pontarelli, S; Maestro, Ja. - In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. - ISSN 1063-8210. - (2012). [10.1109/TVLSI.2012.2230655]

Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation

Pontarelli S;
2012

Abstract

Error correction codes (ECCs) are commonly used to protect memories against errors. Among ECCs, orthogonal latin squares (OLS) codes have gained renewed interest for memory protection due to their modularity and the simplicity of the decoding algorithm that enables low delay implementations. An important issue is that when ECCs are used, the encoder and decoder circuits can also suffer errors. In this brief, a concurrent error detection technique for OLS codes encoders and syndrome computation is proposed and evaluated. The proposed method uses the properties of OLS codes to efficiently implement a parity prediction scheme that detects all errors that affect a single circuit node. © 1993-2012 IEEE.
2012
Error Detection; Orthogonal Latin Squares Encoders; Syndrome Computation
01 Pubblicazione su rivista::01a Articolo in rivista
Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation / Reviriego, P; Pontarelli, S; Maestro, Ja. - In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. - ISSN 1063-8210. - (2012). [10.1109/TVLSI.2012.2230655]
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/1523381
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