This paper presents a detailed characterization of the effects of intra-gate resistive open defects on nanoscaled CMOS gates as causing faults with timing and pattern sequence dependency. The values of the least detectable resistance are established for different feature sizes using HSPICE. It is found that as the feature size is reduced, the value of the least detectable resistance increases in the presence of a fault resulting in a delay of less than one nanosecond. The use of a low voltage testing technique is investigated for the detection of these faults. Finally, an analytical model that takes into account the gate current is proposed; this model considers the pronounced effect of the gate current at a decreasing feature size, while incurring in a small error compared with simulation results.

On the effects of intra-gate resistive open defects in gates at nanoscaled CMOS / Rajderkar, N; Ottavi, Marco; Pontarelli, Salvatore; Han, J; Lombardi, F.. - (2011), pp. 309-315. (Intervento presentato al convegno IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)) [10.1109/DFT.2011.51].

On the effects of intra-gate resistive open defects in gates at nanoscaled CMOS

PONTARELLI, SALVATORE;
2011

Abstract

This paper presents a detailed characterization of the effects of intra-gate resistive open defects on nanoscaled CMOS gates as causing faults with timing and pattern sequence dependency. The values of the least detectable resistance are established for different feature sizes using HSPICE. It is found that as the feature size is reduced, the value of the least detectable resistance increases in the presence of a fault resulting in a delay of less than one nanosecond. The use of a low voltage testing technique is investigated for the detection of these faults. Finally, an analytical model that takes into account the gate current is proposed; this model considers the pronounced effect of the gate current at a decreasing feature size, while incurring in a small error compared with simulation results.
2011
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
04 Pubblicazione in atti di convegno::04c Atto di convegno in rivista
On the effects of intra-gate resistive open defects in gates at nanoscaled CMOS / Rajderkar, N; Ottavi, Marco; Pontarelli, Salvatore; Han, J; Lombardi, F.. - (2011), pp. 309-315. (Intervento presentato al convegno IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)) [10.1109/DFT.2011.51].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/1523292
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