This paper proposes two new slave latches for improving the Single Event Upset (SEU) tolerance of a flip- flop in scan delay testing. The two proposed slave latches utilize additional circuitry to increase the critical charge of the flip-flop compared to designs found in the technical literature. The first (second) latch design achieves a 5.6 (2.4) times larger critical charge with 11% (4%) delay and 16 % (9%) power consumption overhead at 32nm feature size as compared to the best design found in the technical literature. Moreover, it is shown that the proposed slave latches have also superior performance in the presence of a single event with a multiple node upset.
On the design of two single event tolerant slave latches for scan delay testing / Lu, Y; Lombardi, F; Pontarelli, S; Ottavi, M. - (2012), pp. 67-72. (Intervento presentato al convegno IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2012) [10.1109/DFT.2012.6378202].
On the design of two single event tolerant slave latches for scan delay testing
Pontarelli S;
2012
Abstract
This paper proposes two new slave latches for improving the Single Event Upset (SEU) tolerance of a flip- flop in scan delay testing. The two proposed slave latches utilize additional circuitry to increase the critical charge of the flip-flop compared to designs found in the technical literature. The first (second) latch design achieves a 5.6 (2.4) times larger critical charge with 11% (4%) delay and 16 % (9%) power consumption overhead at 32nm feature size as compared to the best design found in the technical literature. Moreover, it is shown that the proposed slave latches have also superior performance in the presence of a single event with a multiple node upset.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
