Secure implementation of TEL-compatible flip-flops using a standard-cell approach

The Time Enclosed Logic (TEL) is a dual-rail signaling protocol used in the context of cryptographic circuits in order to maintain the time enclosing of information leakage also in the presence of capacitive mismatch. The capacitive mismatch, due to non-perfectly balanced differential routing, provides additional data-dependent leakage that a malicious adversary could use to recover secret information from a hardware implementation. In this work, a novel TEL-compatible standard-cell based flip-flop for cryptographic application is presented. The new flip-flop is intended to be compatible also for FPGA applications. The novel standard-cell architecture has been tested with energy-defined metrics adopting a 4-bit register as case study, implemented in 40nm CMOS process. It has been found that it is able to reduce the data-dependence of the power consumption up to ×0.05 also in the presence of strong mismatch if compared to unprotected CMOS. A comparison with WDDL and MDPL has shown that NED and NSD are remarkably reduced (up to ×30 and ×40 respectively), and their values are independent from the capacitive mismatch in the novel flip-flop architecture.