A low-power delta-sigma modulator ADC for sensor system applications

This paper discusses a third-order tri-level quantizer delta-sigma modulator analog-digital converter (ADC) for cascaded integrators with distributed feedback (CIFB) and cascaded integrators with distributed feedforward (CIFF) structure for sensor system applications. The signal transfer function (STF) and noise transfer function (NTF) discussed for poles and zeroes. Oversampling ratio (OSR) and different quantizer level presented for the modulator structure to trade-off the targeted bandwidth and complexity of increased quantizer level. NTF zero optimization technique also implemented to further reduce inband quantization noise by shaping at high frequency, which is later filtered by digital low-pass filter. Mismatch simulation results also performed for quantizer levels considering the performance degradation of the modulator. Operational amplifier (op-amp) for the front-end integrator optimized for minimum power consumption by considering low finite DC-gain, limited slew-rate, minimum required gain-bandwidth product (GBW). The proposed model simulations provided and discussed. Non-ideal effect for the proposed complete modulator CIFF structure for switched-capacitor circuit level implementation performed. The non-ideal parameters like thermal noise, sampling jitter, white noise, and switch nonlinearity also discussed. Modeling simulation results for CIFF structure with trilevel quantizer, shows that proposed modulator structure can achieve signal-to-noise ratio (SNR) of 133dB for sensor system bandwidth of 10kHz with OSR = 128.